The present invention relates to silicon verification generally and, more particularly, to embedding testbenches in silicon for verification.
Testbenches are typically used in simulation to verify functionality. Evaluation boards are typically used in silicon verification to verify functionality on a volume scale. Simulation testbenches are usually constrained by slow simulation time.
Conventional testbench based verification is constrained to simulations only. No graceful link between simulation testbenches and silicon verification is normally provided with conventional systems. Typically, testbenches are hardcoded at the module level with little link to chip level.
Conventional testbenches have the disadvantages of not providing xe2x80x9cat speedxe2x80x9d verification. Additionally, simulation testbenches are slow. Debugging is more difficult with simulation testbenches. At times, significant effort is needed to re-create the debug issue in simulation software.
One aspect of the present invention concerns a system for silicon chip evaluation comprising a chip embedded in a wafer and one or more testbench circuits embedded in the wafer, wherein the one or more testbenches provide verification of the chip. Another aspect of the present invention concerns a method for silicon chip verification comprising the steps of (A) embedding a chip in a silicon wafer, (B) embedding one or more testbench circuits in the silicon wafer, and (C) communicating between the one or more testbenches and the chip to provide silicon verification of the chip.
The objects, features and advantages of the present invention include providing a silicon testbench that may (i) be implemented using design software, (ii) provide xe2x80x9cat speedxe2x80x9d verification of a design by implementing the testbench at the silicon level, and/or (iii) provide verification at the silicon level.